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enpirion ? power datasheet ep53a7lqi/ep53a7hqi 1a powersoc light load mode buck regulator with integrated inductor description the ep53 a7 xq i (x = l or h) is a 1000ma powersoc. the ep53a7xqi integrates mosfet switches, control, compensation, and the magnetics in an advanced 3 mm x 3 mm qfn package. integrated magnetics enables a tiny solution footprint, low output ripple, low part - count, and high reliability, while maintaining high efficiency. the complete solution can be implemented in as little as 21 mm 2 . a proprietary light load mode (llm) provides high efficiency in light load conditions. the ep53a7xqi uses a 3 - pin vid to easily select the output voltage setting. output voltage settings are available in 2 optimized ranges providing coverage for typical v out settings. the vid pins can be changed on the fly for fast dynamic voltage scaling. ep 53a7lqi further has the option to use an external voltage divider. the ep53a7xqi offers the optimal combination of very small solution footprint and advanced performance features. ep 53 a7 xqi 4.7 uf 10uf 6 mm 3.5 mm 100 ohm figure 1: total s olution footprint features ? integrated inductor technology ? 3 mm x 3 mm x 1.1mm qfn package ? total solution footprint < 21 mm 2 ? low v out ripple for rf compatibility ? high efficiency, up to 9 4% ? 10 00ma continuous output current ? 55 a quiescent current ? less than 1 a standby cur rent ? 5 mhz switching frequency ? 3 pin vid for glitch free voltage scaling ? v out range 0.6v to v in ? 0.5v ? short circuit and over current protection ? uvlo and thermal protection ? ic level reliability in a powersoc solution application ? portable w ireless and rf applications ? s olid state storage applications ? space constrained applications requiring high efficiency and very small solution size v in v sense pvin v s1 v s2 v s0 10 f 4.7 f v out v out agnd enable v fb pgnd avin llm 100 ohm figure 2: typical application schematic www.altera.com/enpirion 01543 october 11, 2013 rev d
ep 53 a7 lqi/ep53a7hqi ordering information part number comment package ep 53a7lqi low vid range 16- pin qfn t&r ep 53a7hqi high vid range 16 - pin qfn t&r evb-ep5 3a7lqi ep 53a7lqi evalua tion board e vb-ep53a7hqi ep 53a7hqi evaluation board pin assignments (top view) figure 3: ep 53a7lqi pin out diagram (top view) figure 4 : ep 53a7hqi pin out diagram (top view) pin description pin n am e function 1 , 15, 16 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. nc (sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage to the device. 2 pgnd power ground. connect this pin to the ground electrode of the input and output filter capacitors. 3 llm llm ( light load mode ? ?llm?) pin. logic - high enables automatic llm/pwm and logic - low places the device in fixed pwm operation. 4 vfb nc ep 53a7lqi : feed back pin for external resistor divider option. ep 53a7hqi : no connect 5 vsense sense pin for preset output voltages. refer to application section for proper configuration . 6 agnd analog ground. this is the quiet ground for the inter nal control circuitry, and the ground return for external feedback voltage divider 7, 8 vout regulated output voltage. refer to application section for proper layout and decoupling. 2 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi pin n am e function 9, 10, 11 vs2, vs1, vs0 output voltage select. vs2 = pin 9, vs1 = pin 10 , vs0 = pin 11. ep 53a7lqi : selects one of seven preset output voltages or an external resistor divider. ep 53a7hqi : s elects one of eight preset output voltages. (refer to section on output voltage select for more details.) 12 enable output enable. enable = logic high; disable = logic low 13 avin input power supply for the controller circuitry. connect to pvin through a 100 ohm resistor. 14 pvin input voltage for the mosfet switches. absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating condition s is not implied. stress beyond the absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability . parameter symbol min m ax units input supply voltage v in - 0. 3 6.0 v voltages on: enable , v sense , v so ? v s2 - 0.3 v in + 0.3 v voltages on: v fb (ep 53a7lqi ) - 0. 3 2. 7 v maximum operating junction temperature t j- abs 150 c storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020 c 260 c esd rating (based on h uman b ody m ode ) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2. 4 5.5 v operating ambient temperature t a - 40 +8 5 c operating junction temperature t j - 40 + 125 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient ? 0 lfm ( note 1 ) ja 8 0 c/w thermal overload trip point t j- tp +155 c thermal overload trip point hysteresis 25 c note 1 : based on a four layer copper board and proper thermal design per jedec eij/jesd51 s tandards 3 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi electrical characteristics note: t a = - 40c to +85 c unless otherwise noted. typical values are at t a = 25c, vin = 3.6v . c in = - 4.7 f mlcc , c out = 10 f mlcc parameter symbol test conditions min typ m ax units operating input voltage v in 2. 4 5.5 v under voltage lock - out ? v in rising v uvlo _r 2. 0 v under voltage lock - out ? v in falling v uvlo _f 1.9 v drop out resistance r do input to output resistance 350 500 m ? v out t a = 25 q c , v in = 3.6v; i load = 100ma ; 0.8v v out 3.3 v -2 +2 % feedback pin voltage initial accuracy v fb t a = 25 q c , v in = 3.6v; i load = 100ma ; 0. 8 v v out 3.3v .588 0.6 0.612 v line regulation ' v out_l ine 2.4v v v out_load 0a i load 1000ma 0. 6 %/a temperature variation ' v out_temp l - 40q c t a + 85q c 30 ppm / q c output current i out 1000 ma shut - down current i sd enable = low 0.75 a ep 53a7hqi operating quiescent current i q i load =0; preset output voltages, llm=high 55 a ep 53a7lqi operating quiescent current i q i load =0; preset output voltages, llm=high 65 a ocp threshold i lim 2.4v v v out 3.3 v 1.25 1.4 a feedback pin input current i fb note 1 <100 na vs0 - vs2, pin logic low v vslo 0.0 0.3 v vs0 - vs2, pin logic high v vshi 1.4 v in v vs0 - vs2, pin input current i vsx note 1 <100 na enable pin logic low v enlo 0.3 v enable pin logic high v enhi 1.4 v enable pin current i enable note 1 <100 na llm engage headroom minimum difference between v in and v out to ensure proper llm operation 7 00 mv llm pin logic low v llmlo 0.3 v llm pin logic high v llmhi 1.4 v 4 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi parameter symbol test conditions min typ m ax units llm pin current i llm <100 na operating frequency f osc 5 mhz soft start operation soft start slew rate ? v ss ep53a7lqi (vid only) ep53a7hqi (vid only) 4 8 v/ms soft start rise time ? t ss ep53a7lqi (vfb mode); note 2 170 225 280 s note 1 : parameter guaranteed by design note 2: measured from when v in ? v uvlo_r & enable pin crosses its logic high threshold. typical performance characteristics efficiency vs. load current: v out = 1.2 v, v in (f rom top to bottom) = 2.5, 3.3 , 3.7 , 4.3 , 5.0 v efficiency vs. load current: v out = 1.8 v, v in (f rom top to bottom) = 2.5, 3.3 , 3.7 , 4.3 , 5.0 v efficiency vs. load current: v out = 2.5 v, v in (f rom top to bottom) = 3.3 , 3.7 , 4.3 , 5.0 v efficiency vs. load current: v out = 3.3 v, v in (f rom top to bottom) = 3.7 , 4.3 , 5.0 v 45 50 55 60 65 70 75 80 85 90 95 10 100 1000 load current (ma) efficiency (%) 45 50 55 60 65 70 75 80 85 90 95 10 100 1000 load current (ma) efficiency (%) 45 50 55 60 65 70 75 80 85 90 95 10 100 1000 load current (ma) efficiency (%) 45 50 55 60 65 70 75 80 85 90 95 10 100 1000 load current (ma) efficiency (%) llm llm pwm pwm llm pwm v out =1.2v v out =1.8v v out =2.5v llm pwm v out =3.3v 5 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi start up waveform: v in = 5.0v , v out = 3.3 v; i load = 10ma ; vid mode start up waveform: v in = 5.0v , v out = 3.3 v; i load = 1000ma ; vid mode shut - down waveform: v in = 5.0v , v out = 3.3 v; i load = 10ma, pwm shut - down waveform: v in = 5.0v , v out = 3.3 v; i load = 100 0ma , pwm output ripple: v in = 5 .0 v, v out = 1.2v , load = 10ma llm enabled output ripple: v in = 5 .0 v, v out = 1.2v , load = 1a 50mv/div 5mv/div 6 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi output ripple: v in = 5 .0 v, v out = 3.3 v , load = 10m a llm enabled output ripple: v in = 5 .0 v, v out = 3.3 v , load = 1 a output ripple: v in = 3.3 v, v out = 1. 8v , load = 10ma llm enabled output ripple: v in = 3.3 v, v out = 1. 8v load = 1a output ripple: v in = 3.3 v, v out = 1.2v , load = 10ma llm enabled output ripple: v in = 3.3 v, v out = 1.2v , load = 1a 5mv/div 50mv/div 5mv/div 50mv/div 50mv/div 5mv/div 7 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi load transient: v in = 5.0v, v out = 3.3 v load stepped from 0ma to 1000ma load transient: v in = 5.0v, v out = 3.3 v load stepped from 10ma to 1000 ma, llm enabled load transient: v in = 5.0 v, v out = 1.2 v load stepped from 0ma to 1000ma load transient: v in = 5.0 v, v out = 1. 2v load stepped from 10ma to 1000ma , llm enabled 8 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi load transient: v in = 3.7 v, v out = 1.2 v load stepped from 0ma to 1000ma load transient: v in = 3.7 v, v out = 1.2 v load stepped from 10ma to 1000ma, llm enabled load transient: v in = 3.3 v, v out = 1.8 v load stepped from 0ma to 1000ma load transient: v in = 3.3 v, v out = 1.8 v load stepped from 10ma to 1000ma, llm enabled 9 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi functional block diagram figure 5: functional block diagram dac switch vref (+) (-) error amp v sense v fb v out package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp pvin enable pgnd logic compensation network nc (sw) voltage select vs 0 vs1 avin vs2 agnd mode logic llm 10 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi detailed description functional overview the ep53a7xqi requires only 2 small mlcc capacitors and an 0201 resistor for a complete dc- dc converter solution. the device integrates mosfet switches, pwm controller, gate - drive, compensation, and inductor into a tiny 3mm x 3mm x 1.1mm qfn package. advanced package design, along with the high level of integration, provides very low output ripple and noise. the ep53a7xqi uses voltage mode control for high noise immunity and load matching to adva nced 90nm loads. a 3 - pin vid allows the user to choose from one of 8 output voltage settings. the ep53a7xqi comes with two vid output voltage ranges. the ep 53a7hqi provides v out settings from 1.8v to 3.3v, the ep 53a7lqi provides vid settings from 0.8v to 1.5v, and also has an external resistor divider option to program output setting over the 0.6v to v in - 0.5v range. the ep53a7xqi provides the industry?s highest power density of any 1 a dcdc converter solution. the key enabler of this revolutionary integ ration is altera enpirion?s proprietary power mosfet technology. the advanced mosfet switches are implemented in deep - submicron cmos to supply very low switching loss at high switching frequencies and to allow a high level of integration. the semiconducto r process allows se a mless integration of all switching, control, and compensation circuitry. the proprietary magnetics design provides high - density/high- value magnetics in a very small footprint. altera enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. protection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overlo ad protection. integrated inductor the ep53a7xqi utilizes a proprietary low loss integrated inductor. the integration of the inductor greatly simplifies the power supply design process. the integrated inductor provides the optimal solution to the comple xity, output ripple, and noise that plague low power dcdc converter design. voltage mode control the ep53a7xqi utilizes an integrated type iii compensation network. voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today?s advanced ics. voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. the very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. light load mode (llm) operation the ep53a7xqi uses a proprietary light load mode to provide high efficiency in the low load operating condition. when the llm pin is high, the device is in automatic llm/pwm mode. when the llm pin is low, the device is in pwm mode. in automatic llm/pwm mode, when a light load condition is detected, the device will (1) step v out up by approximately 1.5% above the nominal operating output voltage setting, v nom , and then (2) shut down unnecessary circuitry, and (3) monitor v out . when v out falls below v nom , the device will repeat (1), (2), and (3). the voltage step up, or pre - positioning, improves transient droop when a load transient causes a transition from llm mode to pwm mode. if a load transient occurs, causing v out to fall below the threshold v min , the device will exit llm operation and begin normal pwm operation. figure 6 demonstrates v out behavior during transition into and out of llm operation. 11 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi figure 6 : v out behavior in llm operation figure 7 : v out droop during periodic llm exit many multi - mode dcdc converters suffer from a condition that occurs when the load current increases on ly slowly so that there is no load transient driving v out below the v min threshold (shown in figure 6 ) . in this condition, the device would never exit llm operation. this could adversely affect efficiency and cause unwanted ripple. to prevent this from occurring, the ep53a7xqi periodically exits llm mode into pwm mode and measures the load current. if the load current is above the llm threshold current, the device will remain in pwm mode. if the load current is below the llm threshold, the device will re - enter llm operation. there will be a small droop in v out at the point where the device exits and re - enters llm, as shown in figure 7 . the load current at which the device will enter llm mode is a function of input and output voltage. figure 8 shows the typical value at figure 8 : typical load current for llm engage and disengage versus v out for selected input voltages table 1 : load current below which the device can be certain to be in llm operation. these values are guaranteed by design which the device will enter llm operation. the actual load current at which the device will enter llm operation can vary by +/ - 30%. table 1 shows the minimum load cu rrent below which the device is guaranteed to be in llm operating mode. to ensure normal llm operation, llm mode should be enabled/disabled with specific sequencing. for applications with explicit llm pin control, enable llm after vin ramp up complete; disable llm before vin ramp down. for applications with enable control, tie llm to enable; enable device after vin ramp up complete and disable device before vin ramp v out i out llm ripple pwm ripple v max v nom v min load step llm threshold current vs. vout 0 50 100 150 200 250 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 vout (v) llm threshold (ma) vin=5v (top curve) vin=4.2v vin=3.7v vin=3.3v (bottom curve) 3.3 3.7 4.3 5.0 3.30 105 147 3.00 62 122 156 2.90 89 126 158 2.60 56 106 136 162 2.50 69 111 138 162 2.20 101 120 141 160 2.10 105 122 141 158 1.80 111 124 138 150 1.50 111 120 130 138 1.45 111 119 128 136 1.20 105 111 117 122 1.15 103 108 114 119 1.10 101 106 111 116 1.05 99 104 108 113 0.80 87 89 92 94 vin vout device exits llm, tests load current 12 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi down begins. for devices with enable and llm tied to vin, contact altera applications engineering for specific recommendations . increased output filter capacitance and/or increased bulk capacitance at the load will decrease the magnitude of the llm ripple. refer to the section on output filter capacitance for maximum values of output filter capacitance and the soft - start section for maximum bulk capacitance at the load. note: for proper llm operation the ep53a7xqi requires a minimum difference between v in and v out of 7 00mv. if this condition is not met, the device cannot be assured proper llm operation. note: automatic llm/pwm is not available when using the external resistor divider option for v out programming. soft start internal soft start circuits limit in - rush current when the device starts up from a power down condition or when the ?enable? pin is asserted ?high?. digital control circuitry limits the v out ramp rate to levels that are safe for the power mosfets and the integrated inductor. the ep 53a7hqi has a soft - start slew rate that is twice that of the ep 53a7lqi . when the ep53a7lui is configured in external resistor divider mode, the device has a fixed vout ramp time. therefore, the ramp rate will vary with the output voltage setting. output voltage ramp time is given in the electrical characteristics table. excess bulk cap acitance on the output of the device can cause an over - current condition at startup. the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: ep 53a7lqi : c out_total_ma x = c out _fi lter + c out _bulk = 200uf ep 53a7hqi : c out_total_max = c out _fi lter + c out _bulk = 100uf ep53a7lui in external divider mode: c out_total_max = 2.25x10 -4 /v out farads the nominal value for c out is 10uf. see the applications section for more details. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulling v out low. this condition is maintained for approximately 0.5ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat. under voltag e lockout during initial power up , an under voltage lockout circuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold , the lockout circuitry will again disable the switching. hysteresis is included to prevent chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. not e: the enable pin must not be left floating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the the rmal shutdown temperature , the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 2 5c , the device will go through the normal startup process. 13 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi application information v in v sense pvin v s1 v s2 v s0 10 f 4.7 f v out v out agnd enable pgnd avin llm 100 ohm figure 9: application circuit, ep 53a7hqi . note that all control signals should be connected to an external control signal, avin or agnd. v in v sense pvin v s1 v s2 v s0 10 f 4.7 f v out v out agnd enable v fb pgnd avin llm 100 ohm figure 10 : application circuit, ep 53a7lqi showing the v fb function. output voltage programming the ep53a7xqi utilizes a 3 - pin vid to program the output voltage value. the vid is available in two sets of output vid programming ranges. the vid pins should be connected either to an external control signal, avin or to agnd to avoid noise coupling into the device. the vid pins must not be left floating. the ?low? range is optimized for low voltage applications. it comes with preset vid settings ranging from 0.80v and 1.5v. this vid set also has an external divider option. to specify this vid range, order part n umber ep 53a7lqi . the ?high? vid set provides output voltage settings ranging from 1.8v to 3.3v. this version does not have an external divider option. to specify this vid range, order part number ep 53a7hqi . internally, the output of the vid multiplexer sets the value for the voltage reference dac, which in turn is connected to the non - inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. note: the vid pins must not be left floating. ep 53a7 l low vid range programming the ep 53a7lqi is designed to provide a high degree of flexibility in powering applications that require low v out setti ngs and dynamic voltage scaling (dvs). the device employs a 3- pin vid architecture that allows the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. the vid pin settings can be chan ged on the fly to implement glitch - free voltage scaling. table 2 : ep 53a7lqi vid voltage select settings table 2 shows the vs2 - vs0 pin logic states for the ep 53a7lqi and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage level. a logic ?0? indicates a connection to agnd or to a ?low? logic voltage level. these pins can be either har dwired to avin or agnd or alternatively can be driven by standard logic levels. logic levels are defined in the electrical characteristics table. any level between the logic high and logic low is indeterminate. ep 53a7lqi external voltage divider the external divider option is chosen by connecting vid pins vs2 - vs0 to avin or a logic ?1? or ?high?. the ep 53a7lqi uses a separate feedback pin, v fb , when using the external divider. v sense must be connected to v out as indicated in figure 11 . vs2 vs1 vs0 vout 0 0 0 1.50 0 0 1 1.45 0 1 0 1.20 0 1 1 1.15 1 0 0 1.10 1 0 1 1.05 1 1 0 0.8 1 1 1 ext 14 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi v in v sense v s0 v s2 ep53a7l 10 f 4.7 uf v out v out agnd enable ra rb v fb v s1 pgnd avin pvin llm 100 ohm figure 11 : ep 53a7lqi using external divider the output voltage is selected by the following formula: ( ) rb ra out vv += 16.0 r a must be chosen as 237k ? to maintain loop gain. then r b is given as: ? ? = 6.0 102.142 3 out b v x r v out can be programmed over the range of 0.6v to (v in ? 0.5v). note: dynamic voltage scaling is not allowed between internal preset voltages and external divider. not e: llm is not functional when using the external divider option. tie the llm pin to agnd when using this option . ep 53a7hqi high vid range programming the ep 53a7hqi v out settings are optimized for higher nominal voltages such as those required to power io, rf, or ic memory. the preset voltages range from 1.8v to 3.3v. there are eight (8) preset output voltage settings. the ep 53a7hqi does not have an externa l divider option. as with the ep 53a7lqi , the vid pin settings can be changed while the device is enabled. table 3 shows the vs0 - vs2 pin logic states for the ep 53a7hq i and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage level. a logic ?0? indicates a connection to agnd or to a ?low? logic voltage level. these pins can be either hardwired to avin or agnd o r alternatively can be driven by standard logic levels. logic levels are defined in the electrical characteristics table. any level between the logic high and logic low is indeterminate. these pins must not be left floating. table 3 : ep 53a7hqi vid voltage select settings power - up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets these requirements . pre - bias start - up the e p53a7x qi does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the ep53a7x qi is not pre - biased when the ep53a7x qi is first enabled. input filter capacitor the input filter capacitor requirement is a 4.7 f 0402 or 0603 low esr mlcc capacitor. output filter capacitor the output filter capacitor requirement is a minimum of 10 f 0 805 mlcc. ripple performance can be improved by using 2x10 f 0603 or 2x10 f 0805 mlcc capacitors . the maximum output filter capacitance next to the output pins of the device is 60 f low esr mlcc capacitance. v out has to be sensed at the last output filter capacitor next to the ep53a7xqi . additional bulk capacitance for decoupling and vs2 vs1 vs0 vout 0 0 0 3.3 0 0 1 3.0 0 1 0 2.9 0 1 1 2.6 1 0 0 2.5 1 0 1 2.2 1 1 0 2.1 1 1 1 1.8 15 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi bypass can be placed at the load as long as there is sufficient separation between the v out sense point and the bulk capacitance. the separation provides an inductance that isolates the control loop from the bulk capacitance. note: excess total capacitance on the output (output filter + bulk) can cause an over - current condition at startup. refer to the section on soft - start for the maximum total capacitance on the output. note: the input and o utput capacitor s must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectr ic formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter filter applications. 16 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi layout recommendation figure 12 shows critical components and lay er 1 traces of a recommended minimum footprint ep 53a7 lq i/ep 53a7 hqi layout with enable tied to v in . alternate enable configurations, and other small signal pins need to be connected and routed according to specific customer application. please see the gerbe r files on the altera website www.altera.com/enpirion for exact dimensions and other layers. please refer to figure 12 while reading the layout recommendations in this section. recommendation 1: input and outp ut filter capacitors should be placed on the same side of the pcb, and as close to the ep 53a7 q i package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the ep 53a7 q i should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: input and output grounds are separated until they connect at the pgnd pins. the separation shown on figure 12 between the input and output gnd circuits helps minimize noise coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below the converter and the input/output capacitors. please see the gerber files on the altera website www. altera.com/enpirion . figure 12: top pcb layer critical components and copper for minimum footprint recommendation 4 : multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for heat dissipation. the drill diameter of the vias should be 0.33mm , and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20 - 0.26mm . do not use thermal reliefs or s pokes to connect the vias to the ground plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 12 . these vias connect the input/output filter capacitors to the gnd plane an d help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c out , then put them just outside the capacitors along the gnd. do not use thermal reliefs or spokes to connect these vias to the ground pl ane. recommendation 5 : avin is the power supply for the internal small - signal control circuits. it should be connected to the input voltage at a quiet point. in figure 12 this connection is made with ravin at the input capacitor close to the v in connection . 17 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi recommended pcb footprint figure 12 3: ep 53a7 xqi package pcb footprint 18 www.altera.com/enpirion 01543 october 11, 2013 rev d
ep53 a7 lqi/ep53a7hqi package and mechanical figure 1 4 : e p53a7x qi package dimensions contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.a ltera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 19 www.altera.com/enpirion 01543 october 11, 2013 rev d

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